Technical Field
The present disclosure relates to integrated circuits, and more particularly, to gate stacks for integrated circuit structures which have been implanted with a species, and a method of forming the same.
Related Art
In the integrated circuit industry, continued miniaturization of transistor structures requires changes in processes to achieve desired performance characteristics of the integrated circuit. One such consideration in the overall performance of a transistor is gate induced drain leakage (GIDL). GIDL refers to unwanted leakage of current between the gate and drain terminals of a transistor. GIDL may occur due to a high field-effect in the drain junction of the transistor. GIDL results in a loss of control of the terminals within the transistor devices. Factors that affect GIDL include gate oxide thickness, the drain dopant concentration, the lateral doping gradient, and the applied drain-to-gate voltage. Various processes have been proposed to reduce GIDL in transistors. For example, sources and drains and/or their respective extension regions have been implanted with particular dopants which have the effect of reducing GIDL. However, such processes are complex, costly, and time consuming.